As fabrication technologies for semiconductor memory devices advance to higher integration of memory cells, it is highly likely that more failures will occur in the memory cells. Since the semiconductor memory devices cannot operate reliably with faulty memory cells, they are discarded as bad products. This is very inefficient in terms of yield. One way to get around the failed cell problem is by replacing failed cells with redundancy cells provided in a semiconductor memory device.
In order to perform a repair operation, a test is performed to find faulty memory cells in a semiconductor memory device. A compression parallel test can simultaneously determine whether a plurality of memory cells is faulty. A compression parallel test determines the failure of the memory cells by sequentially selecting sub word lines, storing data of the same logic level in the plurality of memory cells coupled to the selected sub word lines, and reading the data at the same time.
FIG. 1 is a block diagram illustrating the configuration of a conventional semiconductor memory device that performs a repair operation.
Referring to FIG. 1, the conventional semiconductor memory device includes a failure occurrence signal generation unit 7, a failed address latch unit 8, and a repair unit 9.
When a test mode signal TM is asserted, the failure occurrence signal generation unit 7 performs a compression parallel test to generate a failure occurrence signal GIOSUMB that is asserted when a failure occurs in memory cells connected to a sub word line selected by first to thirteenth row addresses XADD<1:13>. The first to thirteenth row addresses XADD<1:13> include first to fifth row addresses XADD<1:5> for selecting thirty-two cell blocks included in the semiconductor memory device, sixth to tenth row addresses XADD<6:10> for selecting thirty-two main word lines included in each cell blocks, and eleventh to thirteenth row addresses XADD<11:13> for eight sub word lines coupled to each main word line. Therefore, in the compression parallel test, the first to thirteenth row addresses XADD<1:13> are counted on a 1-bit basis in order to sequentially select all sub word lines included in the semiconductor memory device, and are inputted to the failure occurrence signal generation unit 7.
The failed address latch unit 8 latches the first to tenth row addresses XADD<1:10> to generate first latch addresses XADDLAT1<1:10> when the failure occurrence signal GIOSUMB is first asserted, and latches the first to tenth row addresses XADD<1:10> to generate second latch addresses XADDLAT2<1:10> when the failure occurrence signal GIOSUMB is asserted a second time.
The repair unit 9 performs a repair operation to substitute redundancy cells for faulty memory cells coupled to the main word line by the first latch addresses XADDLAT1<1:10> and the second latch addresses XADDLAT2<1:10>. Since the first latch addresses XADDLAT1<1:10> and the second latch addresses XADDLAT2<1:10> are generated by latching the first to tenth row addresses XADD<1:10>, they contain information on the main word lines and the cell blocks coupled to the faulty memory cells.
As described above, the conventional semiconductor memory device performs two times the repair operation of latching the first to tenth row addresses XADD<1:10> at two points of time when the failure occurs in the memory cells coupled to the sub word line as the compression parallel test result and replacing the memory cells coupled to the main word lines with the redundancy cells.
However, since the compression parallel test sequentially selects the sub word lines and determines whether the memory cells coupled to the selected sub word lines are faulty, the first latch addresses XADDLAT1<1:10> and the second latch addresses XADDLAT2<1:10> generated by the failed address latch unit 8 may have the same address. In this case, even though the sub word lines coupled to the faulty memory cells are different, the main word lines are identical and thus the repair operation is unnecessarily performed by the same main word line, causing degradation in repair efficiency.